Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays

The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has significant effect on not only the flexibility resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored maintain efficiency performance across variety evolving applications. This paper presents Canal, Python-embedded domain-specific language (eDSL) compiler for specifying generating interconnects CGRAs. Canal uses graph-based intermediate representation (IR) allows easy hardware generation tight integration with place route tools. We evaluate by constructing both fully static hybrid ready-valid signaling, conducting design space exploration modifying switch box topology, number routing tracks, tile connections. Through use IR CGRA interconnects, eDSL, system, enables fast creation interconnects.